FIG. 8 is a circuit block diagram of conventional switch circuit 1. FIGS. 9A and 9B are timing charts illustrating an operation of conventional switch circuit 1.
In switch circuit 1, power semiconductor 3 is connected to drive circuit 2. Switch circuit 1 includes switches 5 and 6 connected to direct-current (DC) power source 4 and supplies turn-on signals and turn-off signals alternately to gate terminal 7 of power semiconductor 3. Drive circuit 2 is includes controller 8. Controller 8 inputs control signals SAA and SBB to switches 5 and 6 to turn on switch 5 and turn off switch 6, respectively, simultaneously to supplying of the turn-on signal to gate terminal 7. Controller 8 turns off switch 5 and turns on switch 6 simultaneously by similarly inputting control signals SAA and SBB to switches 5 and 6, respectively, for supplying the turn-off signal to gate terminal 7. The timing chart shown in FIG. 9A illustrates the above-described normal operation.
Gate terminal 7 is connected to switch 9 that is connected to switch 6. Switch 9 allows power semiconductor 3 to be turned off softly when an overcurrent flows through power semiconductor 3. The timing chart of FIG. 9B illustrates this operation that is a tri-state operation executed when the overcurrent is detected. The turn-on signal supplied to gate terminal 7 of power semiconductor 3 causes current Ids to flow across a drain terminal and a source terminal of power semiconductor 3. When flowing current Ids increases excessively at time point t1s for some reason, controller 8 inputs control signals SAA and SCC to switches 5 and 9 to turn off switch 5 and to turn on switch 9, respectively.
Upon being tuned on, switch 9 has a higher impedance than switches 5 and 6 which are tuned on. Power semiconductor 3 has a parasitic capacitance exists between gate terminal 7 and the source terminal thereof. When switch 5 is turned off and switch 9 is turned off due to excessive large current Ids, a charge stored in the parasitic capacitance flows through the impedance of switch 9 so as to decrease a voltage at gate terminal 7 gradually. Current Ids accordingly decreases gradually rather than steeply. This operation thus suppresses a surge voltage across the drain terminal and the source terminal by a reactance component in drive circuit 2.
A conventional switch circuit similar to switch circuit 1 is disclosed, for example, in PTL 1.